Static-Noise Margin Analysis of MOS SRAM Cells
نویسنده
چکیده
,4bsfrad —The stability of both resistor-load (R-load) and full-(2MOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting tbe effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are iir good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-load cells at a low supply voltage.
منابع مشابه
Comparative Analysis of Sram Cell Designs in Nano-scale Technology
Bias Temperature Instability (BTI) is a major reliability issue in Nano-Scale CMOS circuits. BTI effect results in the threshold voltage increase of MOS devices over time. Given the Process, Voltage, and Temperature (PVT) dependence of BTI effect, and the significant amount of PVT variations in Nano-scale CMOS, we propose a method of combining the effects of PVT variations and the BTI effect fo...
متن کاملSRAM Cell Performance in Deep Submicron Technology
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power Consumption and propagation delay .Here we have analyzed both read margin for read ability and write margin for SRAM write ability. Static Noise Margin affects both read margin and write margin. We have analyzed the Static Noise Margin using traditional butterfly method which requires the rotati...
متن کاملInvestigation of the Impact of Random Dopant Fluctuation on Static Noise Margin of 22nm SRAM
In this paper, the impact of RDF on the static noise margin (SNM) and read current margin (SINM) of a prototype 22nm 6T SRAM was investigated using TCAD modeling. Individual device statistics of threshold voltages (Vt) and transport related parameters were first extracted for NFETs and PFETs. SNM and SINM characteristics of the corresponding SRAM cells were then analyzed. Two methods to emulate...
متن کاملA 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation
This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y -access MOS (column-direction access transistor) can improve dummy-read cells’ noise margin and isolate the pre-charge noise from bit-lines in synchronous ...
متن کاملUltra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications
Abstract: An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in s...
متن کامل